Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in chip circuit density produce a corresponding emphasis on overall chip packaging strategies in order to remain competitive. Chip and chip carrier manufacturers are therefore constantly being challenged to improve the quality of their products by identifying and eliminating problems, reducing package size and weight, decreasing package costs, providing improved thermal efficiencies and better and more advanced chips. Whereas significant improvements are being made to eliminate systematic problems by reducing process variability, process improvements alone are not sufficient to eliminate all the problems which effect both performance and reliability.
One way to provide a high level of environmental protection for a package is to have a hermetic seal. Of course, preserving module reworkability is a cost advantage, especially for multi-chip modules (MCMs).
One method to obtain a hermetic seal is by using a solder seal. For traditional solder seal packages to be reliable, it is necessary for modules to use expansion matched components, that is, that when the module is powered on, the expansion of the cap at the seal closely matches the expansion of the substrate at the seal. In early solder seal packages, chip powers were low, and the module was fairly isothermal, so expansions were matched by matching the cap's thermal coefficient of expansion (TCE) to the substrate's TCE. This was often done using the same material for both substrate and cap or cover. In this manner, ceramic substrates were often sealed to ceramic caps. The seal was very reliable, but the cap was very expensive.
In some applications, the thermal conductivity of ceramic caps is not sufficient, but most materials that have sufficiently high thermal conductivity also have TCE's that are too high for seal reliability requirements.
As module powers have risen, modules are no longer isothermal, and in some applications, the substrate temperatures during use are significantly higher than the cap temperatures. In order for these modules to have matched amounts of expansion at the solder seal, the components have to have different TCE's. The optimum TCE of the cap is a function of the substrate TCE and the module thermal gradients during use. TCE selection is application specific, and this contributes to a high cap cost.
U.S. Pat. No. 4,020,987 (Hascoe) discloses an alloy core having upper and lower thin alloy coatings, which is punched to form a punched solder performing for use in hermetically sealing a container. During reflow all of the solder layers melt and mix together to form a homogeneous seal band.
U.S. Pat. No. 4,291,815 (Gordon, et al.) discloses a ceramic lid assembly which includes an integral heat fusible layer defining a hermetic sealing area provided around the periphery of the ceramic lid for hermetic sealing of semiconductor chips in a flat pack.
U.S. Pat. No. 4,746,583 (Falanga) discloses a ceramic combined cover, where a solder layer in the form of a pre-cut gold-tin solder frame is tack welded onto a gold layer. The gold layer is readily wettable by the solder layer and is also extremely corrosion resistant.
U.S. Pat. No. 5,153,709 (Fukuoka) teaches the joining of a cap to a ceramic substrate using a connection conductor pattern, an annular inorganic insulation layer, an annular metallized layer and eutectic solder.
U.S. Pat. No. 5,244,143 (Ference, et al.) assigned to the assignee of the instant patent application and the disclosure of which is incorporated herein by reference, describes an apparatus and method for injection molding solder mounds onto electronic devices.
U.S. Pat. No. 5,329,160 (Miura) discloses a low-melting brazing metal separated by a gap-creating spacer which is used in joining a cover to a ceramic substrate having sealing metallized portions.
U.S. Pat. No. 5,471,027 (Call, et al.), discloses a method for forming a chip carrier with a single protective encapsulant. He specifically teaches the use of a picture-frame type area, which is only on the top surface and away from the edges of the substrate, to seal the cap or cover or heat sink to the substrate using a cap sealant.
U.S. Pat. No. 5,718,361, (Braun, et al.), assigned to the assignee of the instant patent application and the disclosure of which is incorporated herein by reference, describes an apparatus and method for forming mold for metallic material, where the metallic interconnections in a mold can be used to form structures, such as, for example, solder connections, heat sinks with fins, etc.
U.S. Pat. No. 5,718,367, (Covell, et al.), assigned to the assignee of the instant patent application and the disclosure of which is incorporated herein by reference, describes a mold transfer apparatus and method, where the metallic connections made in the mold can also be used to form structures, such as, for example, heat sinks with fins, etc.
Therefore, one way to maintain hermetic seal reliability, decrease cost and improve package thermal performance, would be to develop a new solder seal that can accommodate greater mismatches in expansions between the cap and the substrate during use.